In order to solve the problem that it is difficult to conduct relatively complete in-line testing for stacked chips in complex production processes and that the traditional probe - based testing method for TSV incurs high testing losses, a connectivity test structure for stacked chips based on boundary scan technology was designed by combining the boundary scan test structure of stacked chips in the IEEE 1838 standard and the mixed-signal boundary scan test structure in the IEEE 1149.4 standard. This test structure mainly includes an analog boundary scan channel composed of an internal test bus, a test bus interface circuit, and an analog switch matrix capable of isolating the TSV from the chip core, a digital/analog channel configurable boundary scan cell, and a series of interface structures adaptable to the boundary scan of stacked chips. FPGA simulation verification shows that the test structure has good controllability and observability in the connectivity testing of stacked chips, especially in the measurement of the electrical characteristics of TSVs, and provides a On-chip testing method for traditional TSV electrical parameter measurement method.