The data gathered through the module needs to be cached, after that it is written to the host machine. Based on the advantage of SDRAM having large capacity and FIFO can be written and read in any time and under any clock, it design the large capacity FIFO based on SDRAM. In the system, the type of FPGA is CycloneII:EP2C35F484I8 designed by ALTERA.It was realized through Verilog and compiled, synthesized and fitterred by software Quartus11.0,the clock can reached 100 MHz. The design is tested on FPGA, under verification and simulation, the rate of large storage FIFO can reached 43.6 MByte/s, the design is already applied in real system, under uncertain input clock and output clock, the minimum utilization of SDRAM is 43%, the maximum utilization is 100%, it can satisfy the system’s demand completely.