基于强化图注意力网络的数字芯片布局方法
2024,32(11):235-242
摘要：在数字芯片设计后端流程中,宏和标准单元的布局是一项耗时的工作,通过机器学习快速有效地提供解决方案能够加快芯片开发的周期,降低人工布局带来的风险；然而布局问题是一个多目标优化问题,目前大多数方法都注重在满足各项指标下最大化减小线长,已换取时钟延迟的降低,忽略了其他指标仍然存在下降的空间,例如良好的拥塞指标有利于降低芯片散热和功耗；针对上述问题,设计一种新的带有密集型奖励函数的深度强化学习框架,将拥塞信息映射到图像中,给出新的特征嵌入模型对版图的全局信息进行多尺度提取,并引入图注意力网络捕获网表的连接关系,采用Advantage Actor Critic(A2C)算法更新策略函数,实现了数字版图的自动布局,并在公共的数字芯片网表基准上验证了该方法的有效性。
关键词：图卷积神经网络;GAT;数字集成电路;深度强化学习;EDA
Digital chip Placement method based on reinforcement map attention network
Abstract：In the back-end process of digital chip design, the placement of macros and standard cells is a time-consuming task, and providing solutions quickly and effectively through machine learning can speed up the chip development cycle and reduce the risk caused by manual placement. However, the placement problem is a multi-objective optimization problem, and most of the current methods focus on maximizing the reduction of line length under meeting various indicators, which has been exchanged for the reduction of clock delay, ignoring that other indicators still have room for decline, such as good congestion indicators are conducive to reducing chip heat dissipation and power consumption; To solve the above problems, a new deep reinforcement learning framework with intensive reward function is designed, which maps congestion information to images, gives a new feature embedding model to extract the global information of the layout at multiple scales, introduces the connection relationship of the graph attention network to capture the netlist, and updates the policy function with the Advantage Actor Critic (A2C) algorithm to realize the automatic placement of the digital landscape. The effectiveness of the proposed method is verified on the public digital chip netlist benchmark.
Key words：CNN; GAT; Digital integrated circuits; EDA,DRL
收稿日期：2023-10-08
基金项目：国家自然科学基金项目（62105296）
